1. Field of the Invention
The present invention relates to a multilayer wiring substrate having a laminate structure in which a plurality of resin insulation layers and a plurality of conductor layers are laminated alternately in multilayer arrangement, and not having a so-called substrate core in a final product, the substrate core carrying build-up layers successively formed on opposite surfaces thereof.
2. Description of Related Art
In association with recent increasing tendency toward higher operation speed and higher functionality of IC chips used as, for example, microprocessors of computers, the number of terminals increases, and the pitch between the terminals tends to become narrower. Generally, a large number of terminals are densely arrayed on the bottom surface of an IC chip and flip-chip-bonded to terminals provided on a motherboard. However, since the terminals of the IC chip differ greatly in pitch from those of the motherboard, difficulty is encountered in bonding the IC chip directly onto the motherboard. Thus, according to an ordinarily employed method, a semiconductor package configured such that the IC chip is mounted on an IC chip mounting wiring substrate is fabricated, and the semiconductor package is mounted on the motherboard.
The IC chip mounting wiring substrate which partially constitutes such a semiconductor package is practicalized in the form of a multilayer substrate configured such that a build-up layer is formed on the front and back surfaces of a substrate core. The substrate core used in the multilayer wiring substrate is, for example, a resin substrate (glass epoxy substrate or the like) formed by impregnating reinforcement fiber with resin. Through utilization of rigidity of the substrate core, resin insulation layers and conductor layers are laminated alternately on the front and back surfaces of the substrate core, thereby forming respective build-up layers. In the multilayer wiring substrate, the substrate core serves as a reinforcement and is formed very thick as compared with the build-up layers. Also, the substrate core has conductor lines (specifically, through-hole conductors, etc.) extending therethrough for electrical communication between the build-up layers formed on the front and back surfaces.
In recent years, in association with implementation of high operation speeds of IC chips, signal frequencies to be used have become those of a high frequency band. In this case, the conductor lines which extend through the substrate core serve as sources of high inductance, leading to the transmission loss of high-frequency signals and the occurrence of circuitry malfunction and thus hindering implementation of high operation speed. In order to solve this problem, there has been proposed a multilayer wiring substrate configured in the form of a core-less wiring substrate having no substrate core. The core-less wiring substrate does not use a substrate core, which is relatively thick, thereby reducing the overall wiring length. Thus, the transmission loss of high-frequency signals is lowered, whereby an IC chip can be operated at high speed.
Incidentally, an IC chip is formed from a semiconductor material whose thermal expansion coefficient is about 2.0 ppm/° C. to 5.0 ppm/° C. (e.g., silicon or the like). Meanwhile, a multilayer wiring substrate is formed from a resin material or the like whose overall thermal expansion coefficient is about 30 ppm/° C. Therefore, the conventional multilayer wiring substrate is greater in thermal expansion coefficient than the IC chip, which brings about the following problem. When solder used for connection between the IC chip and the multilayer wiring substrate is cooled, due to the influence of thermal stress stemming from the difference in thermal expansion coefficient between the material of the IC chip and the material of the multilayer wiring substrate, cracks may be generated in connection portions, and open failure or the like may occur. That is, in the case where the multilayer wiring substrate as described above is configured, there arises a problem in that high yield and reliability cannot be realized.
In order to solve such a problem, a technique of placing an interposer between the multilayer wiring substrate and the IC chip has been proposed (see, for example, Patent Document 1). When this configuration is employed, the difference in thermal expansion coefficient between the multilayer wiring substrate and the IC chip decreases, and cracks become less likely to be produced in connection portions between the multilayer wiring substrate and the IC chip. Therefore, yield increases, and reliability is enhanced.